DDR4 SDRA에서 DQS에 따른 I/O 마진 값의 변화

TSV-Microbump 간에 발생하는 Open Defect의 모델링에 대한 고찰

TSV Pin-hole Test Method using DC Voltage

Retention Test of DIMM Module by Local Heating

DIMM Press-fit Socket pin seating position effect on socket to system board interconnect

An Indirect Diagnosis of VTT Power Rail Defect in DDR3 Memory System by Using Intensive Address Switching Test Algorithms

Retention Time Test on Heavy Ion-Induced SDRAM Devices

A Case Study of JTAG Interface Connection Failure in FPGA System Caused by SMT Defect

Substitutive model of the sense amplifier dynamic 2-cell incorrect read fault of type 1