AC coupled line testing using boundary scan test methodology

Test buffer design and interface mechanism for differential receiver AC/DC boundary scan test

Programmable test pattern and capture mechanism for boundary scan

Clock generation for testing of integrated circuits

Structure and Method for SDRAM dynamic self refresh entry and exit using JTAG

Low cost emulation scheme implemented via clock control JTAG controller in a scan environment

Integrated circuit having clock-line control and method for testing same

Adaptable scan chains for debugging and manufacturing test purposes

A method of testing single-order address memory

Test circuits and methods for built-in testing integrated devices