2004RamP-V
TechnologyChip SizePower SupplyOperating FrequencyProcessing SpeedGateCountsTransistorsPower ConsumptionFunctionsReleased Date0.18 μm 1P 6M CMOS Logic Process6 mm x6 mm3.3V (I/O), 1.8V(Core)200 MHz50M Verticles/s, 50Mpixel/s (Bilinear Texture Filtering)2M Logic Gates96kB SRAM< 155mWFixed-Point Programmable Vertex ShaderSep. 2004
2004Autonomous SRAM with SAC Scheme
TechnologyChip SizeDensityFunctionPower SupplyReleased DateSamsung 80 nm Double-Stacked Cell Technology1152 μ m x 1728 μ m512 Kb- Sensing Internal Status of SRAM- Analyzing the Data and Control Internal Parameters1.6 V (Internal) / 3.3 V (External)Aug. 2004
2004Network-on-Chip with High-speed Serial Links
TechnologyChip SizeFunctionClock FrequencyPower SupplyPower ConsumptionReleased Date0.18 μm DongbuAnam CMOS Technology5 mm x 5 mm- A Network-on-Chip with 3Gbps/wire Serialized On-chipInterconnect Using Adaptive Control Schemes400MHz input, 1.6 ~ 3.0 Gb/s/wire operation1.8V (core), 3.3V (I/O)N/AMay. 2004
2003Analog Front-End for USB-OTG
TechnologyChip SizeFunctionClock FrequencyPower SupplyOutput VoltagePower EfficiencyLoad CurrentReleased Date0.13 μm Samsung 3.3 V CMOS Technology0.5 mm x 0.5 mmAnalog Front-End Compatible with USB On-The-Go500KHz3.3 V5.0 V> 70 %> 30 mAOct. 2003
2003An 800MHz Star-Connected On-Chip Network
TechnologyChip SizeFunctionClock FrequencyPower SupplyPower ConsumptionReleased Date0.18 μm DongnuAnam CMOS Technology5 mm x 5 mmMultimedia SoC with Low-Power On-Chip Network1.6 GHz for On-Chip Network100 MHz for Processors1.8 V (core), 3.3 V (I/O), 0.6 V (Small-swing-Interconnection)On-Chip Network < 51 mWSep. 2003
2003CAMi
TechnologyChip SizeFunctionMemory CapacityPower SupplySearch TimeEnergy EfficiencyReleased Date0.10 μm Samsung CMOS Process Technology4.2 mm x 2.8 mm- Low Power CAM Architecture Including- Hidden Bank Selection Scheme- Match Line Repeater- Sub Match Line- Column Decoding144 Kb1.2 V2.2 ns0.7 fJ/bit/searchAug. 2003
2002Motion Express
TechnologyChip SizeFunctionClock FrequencyTransistor CountsPower SupplyPower ConsumptionReleased Date0.16 μm Hynix CMOS DRAM Technology6 mm x 6 mmA MPEG- 4 acceleration IP for Portable Video Application27 MHz~10,0002.5 V(core), 3.3 V(I/O)< 6 mWOct. 2002
2002RamP- IV
TechnologyChip SizeFunctionClock FrequencyTransistor CountsPower SupplyPower ConsumptionReleased Date0.16 μm Hynix CMOS DRAM Technology6 mm x 6 mm- 3D Graphic Processor for Mobile Application- 132/33 MHz for FAST mode66/16.5 MHz for NORMAL mode33/8.25 MHz for SLOW mode60,000,0002.3 V210 mWOct. 2002
2002An 800MHz Star-Connected On-Chip Network
TechnologyChip SizeFunctionClock FrequencyTransistor CountsPower SupplyPower ConsumptionReleased Date0.16 μm DRAM Technology with 3 AI10.8 mm x 6.0 mm- On-chip packet transaction with plesiochronous communication- Off-chip packet transaction for scalabilitycore @ 800 MHzIP Block @ 200 MHz81,000 (without 1 Kb SRAM)2.3 V264 mWOct. 2002
200210 Gbps/port 8x8 Shared-bus Switch Fabric
TechnologyChip SizeFunctionClock FrequencyTransistor CountsPower SupplyPower ConsumptionReleased Date0.16 μm DRAM Technology with 3 AI4 mm x 9 mm10 Gbps/port 8x8 Shared-bus witch fabric with Hierarchical OutputBuffer200 MHz for Dual port SRAM20 MHz for Embedded DRAM (w/ 512 bits I/O)32 Kb SRAM, 1 Mb DRAM2.3 V240 mWOct. 2002