Negative Capacitance FinFET With Sub-20-mV/decade Subthreshold Slope and Minimal Hysteresis of 0.48 V

Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack

Vertical Tunnel FET: Design Optimization With Triple Metal-Gate Layers

3-D Quasi-Atomistic Model for Line Edge Roughness in Nonplanar MOSFETs

Design for Variation-Immunity in Sub-10-nm Stacked-Nanowire FETs to Suppress LER-induced Random Variations

Performance Booster for Vertical Tunnel Field-Effect Transistor: Field-Enhanced High-kappa Layer

Random Dopant Fluctuation-Induced Threshold Voltage Variation-Immune Ge FinFET With Metal-Interlayer-Semiconductor Source/Drain

Experimental evidence of negative quantum capacitance in topological insulator for sub-60-mV/decade steep switching device

Study of Work-Function Variation in High-kappa/Metal-Gate Gate-All-Around Nanowire MOSFET

Effect of Metal Nitride on Contact Resistivity of Metal-Interlayer-Ge Source/Drain in Sub-10-nm n-Type Ge FinFET