발행물
컨퍼런스
Korea Test Conference
2014
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A Case Study of JTAG Interface Connection Failure in FPGA System Caused by SMT Defect
한국반도체학술대회
2012
면적 효율과 고-해상도의 후-보정이 가능한 CMOS 버니어 딜레이 라인 셀 디자인
ISOCC Chip Design Contest
2010
Implementation of 8051 8-bit Processor with Variable Pipeline Stages
Korean Test Conference
Analysis of VDDmin Shift by Mixed Gate Oxide Breakdown and NBTI in SRAM
ieek Conference
Design of Area Efficient High Resolution CMOS Vernier Delay Line Cell