Active Precharge Hammering to Monitor Displacement Damage Using High-Energy Protons in 3x-nm SDRAM

Temporal and frequency characteristic analysis of margin-related failures caused by an intermittent nano-scale fracture of the solder ball in a BGA package device

Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs

Statistical distributions of row-hammering induced failures in DDR3 components

An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology

Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation (vol 13, 20160627, 2016)

A 65 nm Temporally Hardened Flip-Flop Circuit

Data Margin impact of the 800Mhz DDR3 DIMM pad wear

Single-Event Transient Sensitivity Evaluation of Clock Networks at 28-nm CMOS Technology

Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 x nm technology