Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Stuck Bits Study in DDR3 SDRAMs Using 45-MeV Proton Beam

An SEU-Tolerant DICE Latch Design With Feedback Transistors

Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams

Single Event Resilient Dynamic Logic Designs

Active-Precharge Hammering on a Row Induced Failure in DDR3 SDRAMs under 3x nm Technology

Novel Error Detection Scheme With the Harmonious Use of Parity Codes, Well-Taps, and Interleaving Distance

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication

Memory Reliability Analysis for Multiple Block Effect of Soft Errors