Null Detector Circuit Design Scheme for Detecting Defective AC Coupled Capacitors in Differential Signaling

A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

Low Power Configuration Strategy of TCAM Lookup Table

Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks

Efficient Interconnect Test Patterns for Crosstalk and Static Faults

Analytical Test Buffer Design For Differential Signaling I/O Buffers By Error Syndrome Analysis

A Cost-Effective Design for Testability: Clock Line Control and Test Generation Using Selective Clocking

Quantification of substrate current caused by an individual trap at different locations and energies, prevailing on Si/SiO2 interface or Si substrate of n-MOSFETs